CS4294 Datasheet, PDF (16/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
5.5.3 AC ’97 Register Reset
The third reset mode provides a register reset to the
CS4294. This is available only when the CS4294’s
AC-link is active and the Codec Ready bit is set.
The audio and extended codec subsections may be
reset independently. Any write to Reset (Index 00h)
register will reset the audio subsection while any
write to Extended Codec Stat/Ctrl (Index 3Eh) reg-
ister will reset the Extended Codec subsection. See
the respective register descriptions for additional
information.
5.6 AC-Link Protocol Violation - Loss of
SYNC
The CS4294 is designed to handle SYNC protocol
violations. The following are situations where the
SYNC protocol has been violated:
• The SYNC signal is not sampled high for
exactly 16 BIT_CLK clock cycles at the
start of an audio frame.
• The SYNC signal is not sampled high on
the 256th BIT_CLK clock period after
the previous SYNC assertion.
• The SYNC signal goes active high before
the 256th BIT_CLK clock period after
the previous SYNC assertion.
Upon loss of synchronization with the Controller,
the Codec will mute all analog outputs and clear the
Codec Ready bit in the serial data input frame until
two valid frames are detected. During this detection
period, the Codec will ignore all register reads and
writes and will discontinue the transmission of
PCM capture data.
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