OPA2690 Datasheet, PDF (24/30 Pages) Burr-Brown (TI) – Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable

OPA2690
SBOS238D − JUNE 2002 − REVISED DECEMBER 2004
In normal operation, base current to Q1 is provided
through the 110kΩ resistor, while the emitter current
through the 15kΩ resistor sets up a voltage drop that is
inadequate to turn on the two diodes in Q1’s emitter. As
V_DIS is pulled LOW, additional current is pulled through the
15kΩ resistor, eventually turning on those two diodes
(≈100µA). At this point, any further current pulled out of
V_DIS goes through those diodes holding the emitter-base
voltage of Q1 at approximately 0V. This shuts off the
collector current out of Q1, turning the amplifier off. The
supply current in the disable mode are only those required
to operate the circuit of Figure 17. Additional circuitry
ensures that turn-on time occurs faster than turn-off time
(make-before-break).
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2690 is operating at a
gain of +1, this will show a very high impedance at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R_F + R_G) will appear as the impedance looking back into
the output, but the circuit will still show very high forward
and reverse isolation. If configured as an inverting
amplifier, the input and output will be connected through
the feedback network resistance (R_F + R_G) and the
isolation will be very poor as a result.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 18
shows these glitches for the circuit of Figure 1 with the
input signal at 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 18, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin provides adequate
bandlimiting using just the parasitic input capacitance on
the DIS pin while still ensuring adequate logic level swing.
6
4
V_DIS
2
0
30
Output Voltage
20
V_O = 0
10
0
−10
−20
−30
Time (20ns/div)
Figure 18. Disable/Enable Glitch
24
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THERMAL ANALYSIS
Due to the high output power capability of the OPA2690,
heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired junction
temperature will set the maximum allowed internal power
dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed
150°C.
Operating junction temperature (T_J) is given by
T_A + P_D × q_JA. The total internal power dissipation (P_D) is
the sum of quiescent power (P_DQ) and additional power
dissipated in the output stage (P_DL) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P_DL
depends on the required output signal and load but, for a
grounded resistive load, be at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this condition,
P_DL = V_S2/(4 × R_L), where R_L includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using
an OPA2690ID (SO-8 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature
of +85°C and with both outputs driving a grounded 20Ω
load to +2.5V.
P_D = 10V × 12.6mA + 2 [5²/(4 × (20Ω || 804Ω))] = 766mW
Maximum T_J = +85°C + (0.766W × 125°C/W) = 180°C.
This absolute worst-case condition exceeds the specified
maximum junction temperature. Actual P_DL is normally
less than that considered here. Carefully consider
maximum T_J in your application.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA2690 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25”) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between