CS4270 Datasheet, PDF (24/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
5.1.7 Mode Selection & De-Emphasis
The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz,
is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper
mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0
pin becomes De-emphasis select. Stand-alone definitions of the mode pins are shown in Table 3.
Mode 1
0
0
1
1
Mode 0
0
1
0
1
Mode
Single-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Sample Rate (Fs)
4 kHz - 54 kHz
4 kHz - 54 kHz
50 kHz - 108 kHz
100 kHz - 216 kHz
De-Emphasis
Off
44.1 kHz
Off
Off
Table 3. CS4270 Stand-Alone Mode Control
5.1.8 Serial Audio Interface Format Selection
Either I²S or Left-Justified serial audio data format may be selected in Stand-Alone Mode. The selection
will affect both the input and output format. Placing a 10 kΩ pull-up to VD on the I²S/LJ pin will select the
I²S format, while placing a 10 kΩ pull-down to DGND on the I²S/LJ pin will select the left justified format.
5.2 Control Port Mode
5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode
1. Pull RST low until the power supply, MCLK, and LRCK are stable.
2. Release RST. The control port will be accessible.
3. Initiate a SPI or I²C transaction as described in Section 6.1 or Section 6.2, respectively.
5.2.2 Master / Slave Mode Selection
The CS4270 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal
to Fs and SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.
It is recommended that SCLK be 48x or 64x Fs to maximize system performance.
Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9.
In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by
changing the status of the M/S bits in the Functional Control Register (03h).
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