CS4270 Datasheet, PDF (17/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
t_sdo
-
-
32
ns
t_sdis
16
-
-
ns
t_sdih
20
-
-
ns
17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according to
Table 5, Table 9, and Table 8
LRCK
Output
SCLK
Output
SDOUT
SDIN
t _slr
t _sdo
t _sdis
t _sdih
LRCK
Input
Figure 3. Master Mode Serial Audio Port Timing
SCLK
Input
SDOUT
SDIN
t _slr
t _sdo
tsclkw
t _sdis
t _sdih
Figure 4. Slave Mode Serial Audio Port Timing
DS686A1
17