CS4270 Datasheet, PDF (22/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

5. APPLICATIONS
CS4270
5.1 Stand-Alone Mode
5.1.1 Recommended Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks
and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital
supplies drop below the minimum specified operating voltages to prevent power glitch related issues.
5.1.2 Master/Slave Mode
The CS4270 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal
to Fs and SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.
It is recommended that SCLK be 48x or 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4270 will enter Slave Mode when SDOUT (M/S) is pulled low through a 47
kΩ resistor. Master Mode may be accessed by placing a 47 kΩ pull-up to VD on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes is outlined in Table 2.
5.1.3 System Clocking
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes as shown in Table 1
.
Mode
Single-Speed
Double-Speed
Quad-Speed
Sampling Frequency
4-54 kHz
50-108 kHz
100-216 kHz
Table 1. Speed Modes
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