CS4272 Datasheet, PDF (22/53 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4272
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: logic 0 = AGND, logic 1 = VL)
Parameter
SPI Mode
CCLK Clock Frequency.
RST Rising Edge to CS Falling.
CCLK Edge to CS Falling.
CS High Time Between Transmissions.
CS Falling to CCLK Edge.
CCLK Low Time.
CCLK High Time.
CDIN to CCLK Rising Setup Time.
CCLK Rising to DATA Hold Time.
Rise Time of CCLK and CDIN.
Fall Time of CCLK and CDIN.
Symbol
Min
f_sclk
-
t_srs
500
(Note 24)
t_spi
500
t_csh
1.0
t_css
20
t_scl
82
t_sch
82
t_dsu
40
(Note 25)
t_dh
15
(Note 26)
t_r2
-
(Note 26)
t_f2
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 24. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
25. Data must be held for sufficient time to bridge the transition time of CCLK.
26. For F_SCK < 1 MHz
RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _{dsu t dh}
Figure 7. SPI Control Port Timing
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DS593F1