CS4216 Datasheet, PDF (18/58 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4216
Bits per Frame (Slave Sub-Mode)
In Slave sub-mode, MF1:F1 and MF2:F2 select
the number of bits per frame which determines
how many CS4216’s can occupy one serial port.
Table 4 lists the decoding for MF1:F1 and
MF2:F2.
When set for 64 SCLKs per frame, one device
occupies the entire frame; therefore, a sub-frame
is equivalent to a frame. MF7:SFS1 and
MF8:SFS2 must be set to zero. See Figure 10.
When set for 128 SCLKs per frame, two devices
can occupy the serial port, with MF7:SFS1 se-
lecting the particular sub-frame. MF8:SFS2 must
be set to zero. See Figure 11.
When set for 256 SCLKs per frame (MF1:F1,
MF2:F2 = 10), four devices can occupy the se-
rial port. In this format both MF8:SFS2 and
MF7:SFS1 are used to select the particular sub-
frame. See Figure 12.
In all three of the above Slave sub-mode for-
mats, the frequency of the incoming SCLK
signal, in relation to the master clock provided
on the CLKIN pin, determines the sample fre-
quency. The CS4216 determines the ratio of
SCLK to CLKIN and sets the internal operating
MF1:
F1
0
0
0
0
1
1
1
1
MF2:
F2
0
0
1
1
0
0
1
1
MF3: N
F3
0 256
1 384
0 512
1 640
0 768
1 1024
0 1280
1 1536
Fs (kHz)
with CLKIN
12.288 11.2896
MHz
MHz
48.00 44.10
32.00 29.40
24.00 22.05
19.20 17.64
16.00 14.70
12.00 11.025
9.60
8.82
8.00
7.35
frequency accordingly. Table 5 lists the SCLK to
CLKIN frequency ratio used to determine the
codec’s sample frequency. To obtain a given
sample frequency, SCLK must equal CLKIN di-
vided by the number in the table, based on the
number of bits per frame. As an example, assum-
ing 64 BPF (bits per frame) and
CLKIN = 12.288 MHz, if a sample frequency of
24 kHz is desired, SCLK must equal CLKIN di-
vided by 8 or 1.536 MHz.
When MF1:F1 = MF2:F2 = 1, SCLK is used as
the master clock and is assumed to be 256 times
the sample frequency. In this mode, CLKIN is
ignored and the sample frequency is linearly
scaled with SCLK. (The CLKIN pin must be
tied low.) This mode also fixes SCLK at 256 bits
per frame with MF7:SFS1 and MF8:SFS2 select-
ing the particular sub-frame.
MF1: MF2: Bits per Sample Frequency/
F1 F2 Frame
SCLK
0
0
64
ratio to CLKIN sensed
0
1
128 ratio to CLKIN sensed
1
0
256 ratio to CLKIN sensed
1
1
256
fixed^†. = 256×Fs
† _{SCLK is master clock. CLKIN is not used.}
Table 4. SM3-Slave, Bits per Frame.
SCLK to CLKIN Ratio Fs (kHz) Fs (kHz)
BPF BPF BPF with CLKIN with CLKIN
256 128 64 12.288 MHz 11.2896 MHz
1
2
4
48.00
44.10
1.5
3
6
32.00
29.40
2
4
8
24.00
22.05
2.5
5
10
19.20
17.64
3
6
12
16.00
14.70
4
8
16
12.00
11.025
5
10 20
9.60
8.82
6
12 24
8.00
7.35
Table 3. SM3-Master, Fs Select
Table 5. SM3-Slave, Fs Select.
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DS83F2