CS4216 Datasheet, PDF (16/58 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4216
externally. In Master sub-mode, the serial port
signal transitions are controlled with respect to
the internal analog sampling clock to minimize
the amount of digital noise coupled into the ana-
log section. Since SSYNC and SCLK are
externally derived in Slave sub-mode, optimum
noise management cannot be obtained; therefore,
Master sub-modes should be used whenever pos-
sible.
Master Sub-Mode (SM3)
Master sub-mode is selected by setting
MF4:MA = 1, which configures SSYNC and
SCLK as outputs from the CS4216. During
power down, SSYNC and SCLK are driven high
impedance, and during reset they both are driven
low. In Master sub-mode the number of bits per
frame determines how many codecs can occupy
the serial bus and is illustrated in Figure 8.
Bits Per Frame (Master Sub-Mode)
MF8:SFS2 selects the number of bits per frame.
The two options are MF8:SFS2 = 1 which se-
lects 128 bits per frame, and MF8:SFS2 = 0
which selects 64 bits per frame.
Selecting 128 bits per frame (MF8:SFS2 = 1) al-
lows two CS4216s to operate from the same
serial bus since each codec requires 64 bit peri-
ods. The sub-frame used by an individual codec
is selected using MF7:SFS1. MF7:SFS1 = 0 se-
lects sub-frame 1 which is the first 64 bits
following the SSYNC pulse. MF7:SFS1 = 1 se-
lects sub-frame 2 which is the last 64 bits of the
frame.
Selecting 64 bits per frame (MF8:SFS2 = 0) al-
lows only one CS4216 to occupy the serial port.
Since there is only one sub-frame (which is
equal to one frame), MF7:SFS1 is defined differ-
ently in this mode. MF7:SFS1 selects the format
of SSYNC. MF7:SFS1 = 0 selects an SSYNC
pulse one SCLK period high, directly preceding
the data as shown in the center portion of Fig-
16
ure 8. This format is used for all other Master
and Slave sub-modes in SM3. If MF7:SFS1 = 1,
an alternate SSYNC format is chosen in which
SSYNC is high during the entire Word A
(32 bits), which includes the left sample, and
low for the entire Word B (32 bits), which in-
cludes the right sample. This alternate format for
SSYNC is illustrated in the bottom portion of
Figure 8 and is only available in Master sub-
mode with 64 bits per frame. A more detailed
timing diagram for the 64 bits-per-frame Master
sub-mode is shown in Figure 9.
Sample Frequency Selection (Master Sub-Mode)
In SM3, Master sub-mode, the multifunction
pins MF1:F1, MF2:F2, and MF3:F3 are used to
select the sample frequency divider. Table 3 lists
the decoding for the sample frequency select
pins where the sample frequency selected is
CLKIN/N. Also shown are the sample frequen-
cies obtained by using one of two example
master clocks: either 12.288 MHz or
11.2896 MHz. The codec must be reset when
changing sample frequencies to allow the codec
to calibrate to the new sample frequency.
Slave Sub-Mode (SM3)
In SM3, Slave sub-mode is selected by setting
MF4:MA = 0 which configures SSYNC and
SCLK as inputs to the CS4216. These two sig-
nals must be externally derived from CLKIN. In
Slave sub-mode, the phase relationship between
SCLK/SSYNC and CLKIN cannot be controlled
since SCLK and SSYNC are externally derived.
Therefore, the noise performance may be slightly
worse than when using the master sub-mode.
The number of sub-frames on the serial port is
selected using MF1:F1 and MF2:F2. In Slave
sub-mode MF3:F3 works as a general purpose
input. Figures 10 through 12 illustrate the Slave
sub-mode formats.
DS83F2