OPA2686 Datasheet, PDF (16/18 Pages) Burr-Brown (TI) – Dual, Wideband, Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER

a capacitive load is placed directly on the output pin. When
the amplifier’s open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop re-
sponse, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Performance Curves show the recommended
R_S vs Capacitive Load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA2686. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA2686 output
pin (see Board Layout Guidelines).
The criterion for setting this R_S resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA2686 operating in a gain of +10, the frequency response
at the output pin is very flat to begin with, allowing relatively
small values of R_S to be used for low capacitive loads. As the
signal gain is increased, the unloaded phase margin will also
increase. Driving capacitive loads at higher gains will re-
quire lower R_S values than those shown for a gain of +10.
DISTORTION PERFORMANCE
The OPA2686 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots in the Typical Performance Curves
show the typical distortion under a wide variety of condi-
tions. Most of these plots are limited to 110dB dynamic
range.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd harmonic will dominate the
distortion with negligible a 3rd harmonic component. Focus-
ing then on the 2nd harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network; in the non-inverting configu-
ration, this is sum of R_F + R_G, while in the inverting
configuration, it is just R_F (Figures 1 and 2). Increasing
output voltage swing increases harmonic distortion directly.
A 6dB increase in output swing will generally increase the
2nd harmonic 12dB and the 3rd harmonic 18dB. Increasing
the signal gain will also increase the 2nd harmonic distor-
tion. Again, a 6dB increase in gain will increase the 2nd and
3rd harmonic by approximately 6dB even with constant
output power and frequency. Finally, the distortion increases
as the fundamental frequency increases due to the rolloff in
the loop gain with frequency. Conversely, the distortion will
improve going to lower frequencies down to the dominant
open-loop pole at approximately 100kHz. Starting from the
–82dBc 2nd harmonic for a 5MHz, 2Vp-p fundamental into
a 200Ω load at G = +10 (from the Typical Performance
Curves), the 2nd harmonic distortion for frequencies lower
than 100kHz will be approximately –82dBc – 20log(5MHz/
100kHz) = –116dBc.
The OPA2686 has extremely low 3rd-order harmonic dis-
tortion. This also gives a high two-tone, 3rd-order
intermodulation intercept as shown in the Typical Perfor-
mance Curves. This intercept curve is defined at the 50Ω
load when driven through a 50Ω matching resistor to allow
direct comparisons to RF MMIC devices. This matching
network attenuates the voltage swing from the output pin to
the load by 6dB. If the OPA2686 drives directly into the
input of a high impedance device, such as an ADC, the 6dB
attenuation is not taken. Under these conditions, the inter-
cept will increase by a minimum 6dBm. The intercept is
used to predict the intermodulation spurious for two, closely-
spaced frequencies. If the two test frequencies, f₁ and f₂, are
specified in terms of average and delta frequency, f_O =
(f₁ + f₂)/2 and ∆f = |f₂ – f₁|/2, the two 3rd-order, close-in
spurious tones will appear at f_O ±3 • ∆f. The difference
between two equal test-tone power levels and these
intermodulation spurious power levels is given by
∆dBc = 2 • (IM3 – P_O) where IM3 is the intercept taken
from the Typical Performance Curve and P_O is the power
level in dBm at the 50Ω load for one of the two closely-
spaced test frequencies. For instance, at 5MHz the OPA2686
at a gain of +10 has an intercept of 48dBm at a matched 50Ω
load. If the full envelope of the two frequencies needs to be
2Vp-p, this requires each tone to be 4dBm. The 3rd-order
intermodulation spurious tones will then be 2 • (48 – 4) =
88dBc below the test-tone power level (–84dBm). If this
same 2Vp-p, two-tone envelope were delivered directly into
the input of an ADC—without the matching loss or the
loading of the 50Ω network—the intercept would increase
to at least 54dBm. With the same signal and gain condi-
tions, but now driving directly into a light load, the spurious
tones will then be at least 2 • (54 – 4) = 100dBc below the
4dBm test-tone power levels centered on 5MHz.
DC ACCURACY AND OFFSET CONTROL
The OPA2686 can provide excellent DC signal accuracy
due to its high open-loop gain, high common-mode rejec-
tion, high power supply rejection, and low input offset
voltage and bias current offset errors. To take full advantage
of its low ±1.5mV input offset voltage, careful attention to
input bias current cancellation is also required. The low
noise input stage of the OPA2686 has a relatively high input
bias current (10µA typical into the pins) but with a very
close match between the two input currents—typically
±100nA input offset current. The total output offset voltage
may be reduced considerably by matching the source im-
pedances looking out of the two inputs. For example, one
way to add bias current cancellation to the circuit of Figure
1 would be to insert a 20Ω series resistor into the non-
inverting input from the 50Ω terminating resistor. When the
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OPA2686
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