DAC8871 Datasheet, PDF (15/19 Pages) Burr-Brown (TI) – 16-Bit, Single-Channel, ±18V Output (Unbuffered), Ultra-Low Power, Serial Interface DIGITAL-TO-ANALOG CONVERTER

DAC8871
www.ti.com
SBAS396 – JUNE 2007
THEORY OF OPERATION (continued)
POWER-ON RESET AND HARDWARE RESET
The DAC8871 has a power-on reset function. When the RSTSEL pin is low (tied to DGND), and after power-on
or a hardware reset signal is applied to the RST pin, the DAC latch is cleared ('0') and the V_OUT pin is set to
negative full-scale. When RSTSEL is high, the DAC latch and V_OUT are set to mid-scale.
SERIAL INTERFACE
The DAC8871 digital interface is a standard 3-wire connection compatible with SPI, QSPI™, Microwire™ and TI
DSP™ interfaces, which can operate at speeds up to 50 Mbits/second. The data transfer is framed by the chip
select (CS) signal. The DAC works as a bus slave. The bus master generates the synchronize clock (SCLK) and
initiates the transmission. When CS is high, the DAC is not accessed, and SCLK and SDI are ignored. The bus
master accesses the DAC by driving CS low. Immediately following the high-to-low transition of CS, the serial
input data on the SDI pin are shifted out from the bus master synchronously on the falling edge of SCLK and
latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high transition of CS
transfers the content of the input shift register to the input register.
All data registers are 16 bits. It takes 16 SCLK cycles to transfer one data word to the device. To complete a
whole data word, CS must be taken high immediately after the 16th SCLK is clocked in. If more than 16 SCLK
cycles are applied while CS is low, the last 16 bits are transferred into the input register on the rising edge of
CS. However, if CS is not kept low during the entire 16 SCLK cycles, the data are corrupted. In this case, reload
the DAC latch with a new 16-bit word.
The DAC8871 has an LDAC pin that allows the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be kept high while CS is low. If LDAC is permanently tied low, the
DAC latch will be updated immediately after the input register is loaded (caused by the low-to-high transition of
CS).
EXTERNAL AMPLIFIER SELECTION
The output of the DAC8871 is unbuffered. The output impedance is approximately 6.2kΩ. If the applications
require an external buffer amplifier, the selected amplifier must have a low-offset voltage (1LSB = 305µV for
±10V output range), eliminating the need for output offset trims. Input bias current should also be low because
the bias current multiplied by the DAC output impedance (approximately 6.25kΩ) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. The output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3dB bandwidth of 1MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3dB amplifier
bandwidth results in a shorter effective settling time of the DAC and amplifier combination.
V_SS
V_CC
V_DD DGND V_REFH-S V_REFH-F V_REFL-F V_REFL-S
RSTSEL
RST
LDAC
Control
Logic
CS
SCLK
SDI
Serial
Interface
DAC
V_OUT
AGND
Input
Data
Register
DAC
Latch
DAC8871
Figure 39. DAC8871 with External Amplifier
+V _OPA277
or
OPA211
-V
6.2kW
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