DRV101 Datasheet, PDF (10/19 Pages) Burr-Brown (TI) – PWM SOLENOID/VALVE DRIVER

Voltage Controlled Duty Cycle
Duty cycle can also be programmed with an analog voltage,
V_PWM. With V_PWM ≈ 0.75V, duty cycle is near 90%. Increas-
ing this voltage results in decreased duty cycles. Table II
provides V_PWM values for typical duty cycles. See the “Duty
Cycle vs Voltage” Typical Performance Curve for addi-
tional duty cycles.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 4) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
V_S
5
DRV101
6
Out
PWM
4
V_PWM 3
1kΩ⁽¹⁾
D/A
Converter
(or analog
voltage)
NOTE: (1) Required if voltage source can go below 0.1V.
FIGURE 4. Using a Voltage to Program Duty Cycle.
The DRV101’s internal 24kHz oscillator sets the PWM
period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200µA current
source and connects to the input of a comparator and a 19kΩ
resistor as shown in Figure 5. The DRV101’s PWM control
design is inherently monotonic. That is, a decreased voltage
(or resistor value) always produces an increased duty cycle.
3.8V
f = 24kHz
0.7V
Comparator
V_S
200µA
STATUS FLAG
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a
fault condition, Flag output is driven low (pin voltage
typically drops to 0.3V). A pull-up resistor, as shown in
Figure 6, is required to interface with standard logic. A small
value capacitor may be needed between Flag and ground in
noisy applications.
Figure 6 gives an example of a non-latching fault monitoring
circuit, while Figure 7 provides a latching version. The Flag
pin can sink several milliamps, sufficent to drive external
logic circuitry or an LED (Figure 8) to indicate when a fault
has occurred. In addition, the Flag pin can be used to turn off
other DRV101’s in a system for chain fault protection.
+5V
5kΩ
Pull-Up
TTL or HCT
Flag 7
Thermal Shutdown
Over/Under Current
6
Out
DRV101
4
FIGURE 6. Non-Latching Fault Monitoring Circuit.
Flag
Flag
Flag Reset
74XX76A
V_S
Q
J
Q
CLR CLK
GND K
+5V
20kΩ
(1)
Flag 7
DRV101
19kΩ
Thermal Shutdown
Over/Under Current
6
Out
3
Duty Cycle
Adjust
Resistor or
Voltage Source⁽¹⁾
NOTE: (1) Do not drive pin below 0.1V.
DRV101
4
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
FIGURE 5. Simplified Circuit Model of the Duty Cycle FIGURE 7. Latching Fault Monitoring Circuit.
Adjust Pin.
®
DRV101
10