BS616LV2019 Datasheet, PDF (4/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 128K X 16 bit

BSI
„ LOW V_CC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR ≥ 1.5V
CE ≥ Vcc - 0.2V
BS616LV2019
Vcc
tR
VIH
„AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
Output Load
0.5Vcc
CL = 100pF+1TTL
CL = 30pF+1TTL
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85^oC )
READ CYCLE (48B BGA ignore CE2 condition)
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1 , 2
t (1)
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
55 --
--
--
-- 55
(CE,CE2) --
-- 55
(LB,UB) --
-- 30
--
-- 30
(CE,CE2) 10 --
--
(LB,UB) 10 --
--
5
--
--
(CE,CE2) --
--
30
(LB,UB) --
--
30
--
--
25
10 --
--
CYCLE TIME : 70ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
70 --
--
--
-- 70
--
-- 70
--
-- 35
--
-- 35
10 --
--
10 --
--
5
--
--
--
--
35
--
--
35
--
--
30
10 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV2019
4
Revision 1.2
May 2004