BS616LV2019 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 128K X 16 bit

B S I ^{Very Low Power/Voltage CMOS SRAM}
128K X 16 bit
BS616LV2019
„ FEATURES
• Vcc operation voltage range : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 23mA (@55ns) operating current
I -grade: 25mA (@55ns) operating current
C-grade: 15mA (@70ns) operating current
I -grade: 16mA (@70ns) operating current
0.3uA(Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616LV2019 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V /25^oC and maximum access time of 55ns at 2.7V / 85^oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form , JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2019DC
BS616LV2019TC
BS616LV2019AC
BS616LV2019DI
BS616LV2019TI
BS616LV2019AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 2.7~3.6V
70ns: 2.7~3.6V
+0 ^O C to +70 ^O C 2.7V ~3.6V 55/70
-40 ^O C to +85 ^O C 2.7V ~ 3.6V 55/70
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
55ns
70ns
3.0uA
23mA
15mA
5.0uA
25mA
16mA
PKG TYPE
DICE
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
„ PIN CONFIGURATIONS
A15 1
A14
A13
A12
A11
A10
A9
A8
NC 9
NC 10
/WE
CE2
NC 13
/UB
/LB
NC 16
NC 17
A7
A6
A5
A4
A3
A2
A1 24
BS616LV2019TC
BS616LV2019TI
1
2
3
4
5
6
A
LB OE A0 A1 A2 N.C.
B
D8 UB A3 A4 CE D0
C
D9 D10 A5 A6 D1 D2
D
VSS D11 N.C. A7 D3 VCC
E
VCC D12 N.C. A16 D4 VSS
F
D14 D13 A14 A15 D5 D6
G
D15 N.C. A12 A13 WE D7
H
N.C. A8 A9 A10 A11 ^N.C.
48 A16
47 NC
46 VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
37 VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
27 VSS
/CE
25 A0
„ BLOCK DIAGRAM
A8
A13
A15
Address
A16
20
1024
A14
Input
Row
A12
A7
Buffer
Decoder
A6
A5
A4
16
DQ0
.
.
Data
Input
16
Buffer
.
.
.
.
16
.
.
Data
Output
16
DQ15
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE2 ,CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2019
1
Revision 1.2
May 2004