K1050G Datasheet, PDF (2/5 Pages) Galaxy Semi-Conductor Holdings Limited – SIDAC

RATINGS AND CHARACTERISTIC CURVES
KG --- SERIES
V-I CHARACTERISTICS
+I
IT
RS
IH
IS
IDRM ^IBO
-V
+V
(VBO-VS)
RS _(IS-IBO)
VBO
VT
VS
VDRM
FIG.1-- PEAK SURGE CURRENT vs SURGE CURRENT
FFFFFFFF DURATION
100
SUPPLY FREQUENCY: 60 Hz Sinusoidal
LOAD: Resistive
40
RMS ON-STATE CURRENT: IT RMS Maximum Rated
Value at Specified Junction Temperature
20
10
8.0
6.0
BLOCKING CAPABILITY MAY BE LOST
4.0 _{DURING AND IMMEDIATELY}
FOLLOWING SURGE CURRENT
INTERVAL
2.0
OVERLOAD MAY NOT BE REPEATED
UNTIL JUNCTION TEMPERATURE
HAS RETURNED TO STEADY-STATE
RATED VALUE.
1.0
1.0
10
100
1000
Surge Current Duration - Full Cycles
Specific Test Conditions
di/dt — Critical rate-of-rise of on-state current
dv/dt — Critical rate-of-rise of off-state voltage at rated V_DRM; T_J
100°C
I_BO — Breakover current 50/60 Hz sine w ave
I_DRM — Repetitive peak off-state current 50/60 Hz sine w ave; V = V_DRM
I_H — Dynamic holding current 50/60 Hz sine w ave; R = 100
I_T(RMS) — On-state RMS current T_J 125°C 50/60 Hz sine w ave
I_TSM — Peak one cycle surge current 50/60 Hz sine w ave (nonrepetitive)
R_S — Sw itching resistance
R_S=
(V_BO-V_S)
(I_S-I_BO)
50/60 Hz sine w ave
V_BO — Breakover voltage 50/60 Hz sine w ave
V_DRM — Repetitive peak off-state voltage
V_TM — Peak on-state voltage, I_T = 1 Amp
General Notes
All measurements are made at 60Hz w ith a resistive load at an
ambient temperature of +25°C unless otherw ise specified.
Storage temperature range (T_S) is -65°C to +150°C.
The case (T_C) or lead (T_L) temperature is measured as show n on
the dimensional outline draw ings. See “Package Dimensions” section
of this catalog.
Junction temperature range (T_J) is -40°C to +125°C.
Lead solder temperature is a maximum of +230°C for 10 seconds
maximum; 1/16" (1.59mm) from case.
Electrical Specification Notes
(1) See Figure 9.5 for V_BO change vs junction temperature.
(2) See Figure 9.6 for IBO vs junction temperature.
(3) See Figure 9.2 for I_H vs case temperature.
(4) See Figure 9.13 for test circuit.
(5) See Figure 9.1 for more than one full cycle rating.
(6) R_θJA Type 41 is 70° C/W.
(7) T_L 100°C
(8) See Figure 9.14 for clarification of Sidac operation.
(9) For best Sidac operation, the load impedance should be near or
less than sw itching resistance.
Document Number 0290001
BLGALAXY ELECTRICAL
www.galaxycn.com
2.