AZP52 Datasheet, PDF (5/9 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider

Arizona Microtek, Inc.
DUAL SUPPLY LVPECL OUTPUT TERMINATION
AZP52
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Divider
The standard LVPECL loads are a pair of 50Ω resistors connected between the outputs and V_DD-2.0V (Figure 4). The
resistors provide both the DC and the AC loads, assuming 50Ω interconnect. If an additional supply is available within the
application, a four resistor termination configuration is possible (Figure 5).
Output
Stage
V_bp ^M1
V_DD (+3.3 V)
M2
21.1mA
21.1mA
21.1mA - High
D
M3
M4 _{5.1mA - Low}
V_DD (+3.3 V) _External
Circuitry
130Ω
130Ω
Q
Q
82Ω
82Ω
V_bn
M5
16mA
Figure 5 - Dual Supply Output Termination
THREE RESISTOR TERMINATION
Another termination variant eliminates the need for the additional supply (Figure 6). Alternately three resistors and
one capacitor accomplish the same termination and reduce power consumption.
Output
Stage
V_bp ^M1
V_DD (+3.3 V)
M2
21.1mA
21.1mA
External
Circuitry
Q
Q
21.1mA - High
D
M3
M4 _{5.1mA - Low}
50Ω
50Ω
V_bn
M5
16mA
0.01µF
50Ω
Figure 6 - Three Resistor Termination
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May 2012, Rev 2.1