AZP52 Datasheet, PDF (2/9 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider

Arizona Microtek, Inc.
AZP52
PIN DESCRIPTION AND CONFIGURATION
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Divider
Table 1 - Pin Description
Pin Name Type
1
V_DD Power
2
GND Power
3
D
Input
4
EN
Input
5
Q
Output
6
Q
Output
Function
Positive Supply
Negative Supply
Sine or CMOS Input
Enable
LVPECL Output
LVPECL Output
V_DD 1
GND 2
D3
6Q
5Q
4 EN
ENGINEERING NOTES
Figure 1 – Pin Configuration
FUNCTIONALITY
The AZP52 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as
active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist
designers in selecting the optimal part for their design.
Table 3 lists the specific AZP52 functional operation.
Figure 2 plots the S-parameters of the D input. S-parameter and IBIS model files for the AZP52 are also available for
download.
Table 2 - AZP51-54 & AZP63 Family
Part Number
AZP51
AZP52
AZP53
AZP54
AZP63
Divide Ratio
÷1
÷2
Selectable ÷1 or ÷2
÷1
Selectable ÷1 or ÷2
EN Logic
active HIGH
active HIGH
selectable
active LOW
selectable
EN pull-
up/pull-down
Pull-up
Pull-up
selectable
Pull-down
selectable
Bandwidth
> 800MHz
> 800MHz
> 800MHz
> 800MHz
≥ 1GHz
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2
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May 2012, Rev 2.1