AZP52 Datasheet, PDF (4/9 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider

Arizona Microtek, Inc.
INPUT TERMINATION
AZP52
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Divider
The D input bias is V_DD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mV_pp ensures the AZP52 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and V_DD without damage or waveform degradation.
Input signal
D
A/R
10kΩ
V_DD/2
Figure 3 - Input Termination
OUTPUT TERMINATION TECHNIQUES
The LVPECL compatible output stage of the AZP52 uses a current drive topology to maximize switching speed as
illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS
current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output
current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output
voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs.
Both Q and Q¯ should always be terminated identically to avoid waveform distortion and circulating current caused by
unsymmetrical loads. This rule should be followed even if only one output is in use.
Output
Stage
V_bp ^M1
V_DD (+3.3 V)
M2
21.1mA
21.1mA
External
Circuitry
Q
Q
21.1mA - High
D
M3
M4 _{5.1mA - Low}
50Ω
50Ω
V_bn
M5
16mA
V_TT = V_DD - 2.0V
Figure 4 - Typical Output Termination
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May 2012, Rev 2.1