AZP94_09 Datasheet, PDF (3/10 Pages) Arizona Microtek, Inc – ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

AZP94
SIGNAL DESCRIPTION
PIN/PAD
D
Q/Q¯
V_BB/D¯
BIAS
EN
EN-SEL
DIV-SEL
V_EE
V_CC
FUNCTION
Data Input
Data Outputs
Reference Voltage Output
Input Bias Return
Enable/Reset Input
Enable Logic Select
Divide Ratio Select
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
EN-SEL
EN
Q
Q¯
NC
CMOS Low or V_EE1
Low Low
NC
CMOS High, V_CC or NC Data Data
V_EE
CMOS Low, V_EE or NC¹ Low Low
V_EE
20kΩ to V_EE
20kΩ to V_EE
CMOS High or V_CC
PECL Low, V_EE or NC¹
PECL High or V_CC
Data
Data
Low
Data
Data
Low
1 _{Counter Reset for ÷2 Ratio}
DIVIDE TRUTH TABLE
DIV-SEL
DIVIDE
RATIO
NC
÷1
V_EE1
÷2
1 _{DIV-SEL connection must}
be ≤1Ω.
June 2009 Rev - 6
TIMING DIAGRAM
www.azmicrotek.com
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