AZP94_09 Datasheet, PDF (1/10 Pages) Arizona Microtek, Inc – ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

AZP94
ARIZONA MICROTEK, INC.
ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs
FEATURES
PACKAGE AVAILABILITY
• Green and RoHS Compliant / Lead (Pb) _PACKAGE
PART NO.
MARKING NOTES
Free Package Available
• 3.0V to 5.5V Operation
• Selectable Divide Ratio
MLP 8 (2x2) Green
/ RoHS Compliant AZP94NAG
/ Lead (Pb) Free
J4G
<Date Code>
1,2
• Selectable Enable Polarity and
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Threshold (CMOS/TTL or PECL)
Tape & Reel.
• Tristate Compatible Outputs
2 Date code format: “Y” for year followed by “WW” for week.
• Input Buffer Powers Down when
Disabled
• Selectable Input Biasing
• High Bandwidth for ≥1GHz
• Available in a MLP 8 (2x2) Package
• S Parameter and IBIS Model Files
Available on Arizona Microtek Website
DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If
DIV-SEL is connected to V_EE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), V_EE, or
connected to V_EE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to V_EE allows the EN pin/pad to
function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected
which enables the outputs whenever EN is left open. When EN-SEL is connected to V_EE, an internal 75kΩ pull-
down resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to V_EE with a 20kΩ resistor will allow the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). The default logic condition can be overridden by connecting the EN to V_CC with an external resistor of
≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to V_EE with
a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for
details.
When the AZP94 is disabled, the Q and Q¯ outputs are forced LOW and the input buffer is powered down to
minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip
outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive
the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel
connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when
the outputs are disabled.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com