C0240QGLA-T Datasheet, PDF (18/23 Pages) AZ Displays – Approval Product Specification

Document No.:

DB6
I/O




DB5
I/O




DB4
I/O




DB3
I/O




DB2
I/O




DB1
I/O




DB0
I/O



Frame-synchronizing signal.

VSYNC
I (VSPL=0 Low active, VSPL=1 High active)



FIX this pin at VSS level if the pin is not used
Line-synchronizing signal.

HSYNC
I (HSPL=0 Low active, HSPL=1 High active)



FIX this pin at VSS level if the pin is not used
Input pin for clock signal of external interface : dot clock.

DOTCLK
I
DPL=0 Display data is fetched at DOTCLK’s rising edge
DPL=1 Display data is fetched at DOTCLK’s falling edge



Fix this pin at VSS level if the pin is not used.
Data enablesignal pin for RGB interface.

ENABLE I
EPL
ENABLE GRAM write
GRAM
address
0
0
Valid
Updated



0
1
Invalid
Held
1
0
Invalid
Held
1
1
Valid
Updated


SDI
(SDIN)
For a serial peripheral interface (SPI), input data is fetched at
I the rising edge of the SCL signal, Fix SDI pin at VSS level if the



pin is not used.

^SDO
For a serial peripheral interface (SPI), serves as the serial data
O output pin (SDO), Successive bits are output at the falling edge



(SDOUT)
of the SCL signal.


CSB
Chip select signal input pin.
I 0= driver IC is selected and can be accessed.



(CS/NCS)
1= driver IC is not selected and cannot be accessed.
Pin function
CPU type
Pin description
Read/Write operation

^RW_WRB
(SCL)
RW
I
WRB
68-system selection pin
0=write 1=read



Write strobe signal.(Input pin)
80_system Data is fetched at the rising
edge.
SCL
SPI
The synchronous clock signal
Register select pin.


RS
I 0=Index/status, 1=instruction parameter, GRAM data



Must be fixed at VDD3 level when not used.
Pin Function CPU type
Pin description

E_RDB
E
I
RDB
68-system
Read/Writeoperation enable
pin



80_system
Read strobe signal.
Read out data at the low level
When SPI mode is selected, fix this pin at VDD3 levle
18