5962-9800101KEC Datasheet, PDF (9/12 Pages) AVAGO TECHNOLOGIES LIMITED – Hermetically Sealed, High Speed, High CMR, Logic Gate Optocouplers

Notes:
1. Each channel.
2. All devices are considered two-terminal devices; I_I-O is measured between all input leads or terminals shorted together and all output
leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. t propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of
PHL
the output pulse. The t propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point
PLH
on the trailing edge of the output pulse.
6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single channel
parameter limits for each channel.
7. CM_L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(V < 0.8 V). CM is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
O
H
high state (V > 2.0 V).
O
8. This is a momentary withstand test, not an operating condition.
9. It is essential that a bypass capacitor (0.01 to 0.1 μF, ceramic) be connected from V to ground. Total lead length between both ends of
CC
this external capacitor and the isolator connections should not exceed 20 mm.
10. No external pull up is required for a high logic state on the enable input.
11. The t enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on
ELH
the trailing edge of the output pulse.
12. The t enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on
EHL
the leading edge of the output pulse.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Sub-
groups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits
specified for all lots not specifically tested.
15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.
18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.
Figure 1. High Level Output Current vs. Tempera- Figure 2. Input-Output Characteristics.
ture.
Figure 3. Input Diode Forward Characteristics.
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