HCPL-4200-300 Datasheet, PDF (8/13 Pages) AVAGO TECHNOLOGIES LIMITED – Optically Coupled 20 mA Current Loop Receiver

Notes:
1. ≤ 1 μs pulse width, 300 pps.
2. Derate linearly above 70°C free air temperature at a rate of 1.6 mW/ °C. Proper application of the derating factors will prevent IC junction
temperatures from exceeding 125°C for ambient temperatures up to 85°C.
3. Derate linearly above 70°C free air temperature at a rate of 3.8 mW/ °C.
4. Derate linearly above 70°C free air temperature at a rate of 4.6 mW/ °C.
5. Duration of output short circuit time shall not exceed 10 ms.
6. The device is considered a two terminal device, pins 1, 2, 3, and 4 are connected together and pins 5, 6, 7, and 8 are connected together.
7. The t propagation delay is measured from the 10 mA level on the leading edge of the input pulse to the 1.3 V level on the leading edge of
PLH
the output pulse.
8. The t propagation delay is measured from the 10 mA level on the trailing edge of the input pulse to the 1.3 V level on the trailing edge of the
PHL
output pulse.
9. The rise time, t , is measured from the 10% to the 90% level on the rising edge of the output logic pulse.
r
10. The fall time, t , is measured from the 90% to the 10% level on the falling edge of the output logic pulse.
f
11. Common mode transient immunity in the logic high level is the maximum (negative) dV /dt on the trailing edge of the common mode pulse,
CM
V , which can be sustained with the output voltage in the logic high state (i.e., V ≥ 2 V).
CM
O
12. Common mode transient immunity in the logic low level is the maximum (positive) dV /dt on the leading edge of the common mode pulse,
CM
V , which can be sustained with the output voltage in the logic low state (i.e., V ≤ 0.8 V).
CM
O
13. Use of a 0.1 μF bypass capacitor connected between pins 5 and 8 is recommended.
14. In accordance with UL 1577, each optocoupler momentary withstand is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1
second (leakage detection current limit, I ≤ 5 μA).
i-o
Figure 2. Typical Output Voltage vs. Loop Cur-
rent.
10
8
6
4
I_HYS
2
0
-50 -25
0
25 50 75 100
T_A – AMBIENT TEMPERATURE –°C
Figure 3. Typical Current Switching Threshold vs. Figure 4. Typical Input Loop Voltage vs. Input
Temperature.
Current.
2.8
2.6
I_I = 20 mA
I_I = 12 mA
2.4
2.2
-50 -25
0
25 50 75 100
T_A – AMBIENT TEMPERATURE –°C
Figure 5. Typical Input Voltage vs. Temperature.
1.0
0.9
V_CC = 4.5 V
0.8
I_I = 3 mA
0.7
I_O = 6.4 mA
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20 0 20 40 60 80 100
T_A – TEMPERATURE –°C
Figure 6. Typical Logic Low Output Voltage vs.
Temperature.
0
-1
-2
-3 ^{VO = 2.7 V}
V_CC = 4.5 V
I_I = 12 mA
-4
-5 ^{VO = 2.4 V}
-6
-7
-8
-60 -40 -20 0 20 40 60 80 100
T_A – TEMPERATURE –°C
Figure 7. Typical Logic High Output Current vs.
Temperature.
8