HCMS-2975_13 Datasheet, PDF (8/16 Pages) AVAGO TECHNOLOGIES LIMITED – High Performance CMOS 5 x 7 Alphanumeric Displays

Display Overview
The HCMS‑29xx series is a family of LED displays driven
by on‑board CMOS ICs. The LEDs are configured as 5 x 7
font characters and are driven in groups of 4 characters
per IC. Each IC consists of a 160‑bit shift register (the Dot
Register), two 7‑bit Control Words, and refresh circuitry.
The Dot Regis­ter contents are mapped on a one‑to‑one
basis to the display. Thus, an individual Dot Register bit
uniquely controls a single LED.
8‑character displays have two ICs that are cascaded. The
Data Out line of the first IC is internally connected to
the Data In line of the second IC forming a 320‑bit Dot
Register. The dis­play’s other control and power lines are
connected directly to both ICs. In 16‑character displays,
each row functions as an independent 8‑character display
with its own 320‑bit Dot Register.
Reset
Reset initializes the Control Registers (sets all Control
Register bits to logic low) and places the display in the
sleep mode. The Reset pin should be con­nected to the
system power‑on reset circuit. The Dot Registers are not
cleared upon power‑on or by Reset. After power‑on, the
Dot Register contents are random; however, Reset will
put the display in sleep mode, there­by blanking the
LEDs. The Control Register and the Control Words are
cleared to all zeros by Reset.
To operate the display after being Reset, load the Dot
Register with logic lows. Then load Control Word 0 with
the desired bright­ness level and set the sleep mode bit
to logic high.
Dot Register
The Dot Register holds the pattern to be displayed by
the LEDs. Data is loaded into the Dot Register according
to the procedure shown in Table 1 and the Write Cycle
Timing Diagram.
First RS is brought low, then CE is brought low. Next,
each successive rising CLK edge will shift in the data
at the D_IN pin. Loading a logic high will turn the cor-
responding LED on; a logic low turns the LED off. When
all 160 bits have been loaded (or 320 bits in an 8‑digit
display), CE is brought to logic high.
When CLK is next brought to logic low, new data is
latched into the display dot drivers. Loading data into
the Dot Register takes place while the previous data is
displayed and eliminates the need to blank the display
while loading data.
Pixel Map
In a 4‑character display, the 160‑bits are arranged as 20
columns by 8 rows. This array can be conceptualized as
four 5 x 8 dot matrix character loca­tions, but only 7 of
the 8 rows have LEDs (see Figures 1 & 2). The bottom
row (row 0) is not used. Thus, latch location 0 is never
displayed. Column 0 controls the left‑most column. Data
from Dot Latch locations 0‑7 determine whether or not
pixels in Column 0 are turned‑on or turned‑off. Therefore,
the lower left pixel is turned‑on when a logic high is
stored in Dot Latch location 1. Characters are loaded
in serially, with the left‑most character being loaded
first and the right‑most character being loaded last. By
loading one character at a time and latching the data
before loading the next character, the figures will appear
to scroll from right to left.
Table 1. Register Truth Table
Function
CLK
CE
RS
Select Dot Register
Not Rising ↑ ↓
L
  Load Dot Register 
   D_IN = HIGH LED = “ON” ↑ ↓
   D_IN = LOWLED = “OFF”
L
X 
Copy Data from Dot Register to Dot Latch
L
H
X
Select Control Register
Not Rising ↑ ↓
H
  Load Control Register^[1,3] ↑ ↓
L
X
  Latch Data to Control Word^[2]
L ↑ ↓
X
Notes:
1.  BIT D₀ of Control Word 1 must have been previously set to Low for serial mode or High for simultane-
ous mode.
2.  Selection of Control Word 1 or Control Word 0 is set by D₇ of the Control Shift Register. The unselect-
ed control word retains its previous value.
3.  Control Word data is loaded Most Significant Bit (D₇) first.