HCMS-2975_13 Datasheet, PDF (11/16 Pages) AVAGO TECHNOLOGIES LIMITED – High Performance CMOS 5 x 7 Alphanumeric Displays

Control Word 1
Loading the Control Register with D₇ = logic high selects
Control Word 1. This Control Word performs two func-
tions: serial/simultaneous data out mode and external
oscillator prescale select (see Table 2).
Serial/Simultaneous Data Output D₀
Bit D₀ of control word 1 is used to switch the mode of
D_OUT between serial and simul­ta­neous data entry during
Control Register writes. The default mode (logic low) is
the serial D_OUT mode. In serial mode, D_OUT is connected
to the last bit (D₇) of the Control Shift Register.
Storing a logic high to bit D₀ changes D_OUT to simulta-
neous mode which affects the Control Register only. In
simul­taneous mode, D_OUT is logically con­nected to D_IN.
This arrange­ment allows multiple ICs to have their Control
Registers written to simul­taneously. For example, for N
ICs in the serial mode, N * 8 clock pulses are needed to
load the same data in all Control Registers. In the simul-
taneous mode, N ICs only need 8 clock pulses to load
the same data in all Control Registers. The propaga­tion
delay from the first IC to the last is N * t_DOUTP.
External Oscillator Prescaler Bit D₁
Bit D₁ of Control Word 1 is used to scale the frequency
of an external Display Oscillator. When this bit is logic
low, the external Display Oscil­la­tor directly sets the inter-
nal display clock rate. When this bit is a logic high, the
external oscilla­tor is divided by 8. This scaled frequency
then sets the internal display clock rate. It takes 512
cycles of the display clock (or 8 x 512 = 4096 cycles of
an external clock with the divide by 8 pre­scaler) to com­
pletely refresh the display once. Using the pre­scaler bit
allows the designer to use a higher external oscillator
fre­quency without extra circuitry.
This bit has no affect on the internal Display Oscillator
Frequency.
Bits D₂‑D₆
These bits must always be pro­grammed to logic low.
Cascaded ICs
Figure 3 shows how two ICs are connected within an
HCMS‑29XX display. The first IC controls the four left‑most
characters and the second IC controls the four right‑most
characters. The Dot Registers are connected in series to
form a 320‑bit dot shift register. The location of pixel 0
has not changed. However, Dot Shift Register bit 0 of IC2
becomes bit 160 of the 320‑bit dot shift register.
The Control Registers of the two ICs are independent
of each other. This means that to adjust the display
brightness the same control word must be entered
into both ICs, unless the Control Registers are set to
simultaneous mode.
Longer character string systems can be built by cascad-
ing multi­ple displays together. This is accomplished by
creating a five line bus. This bus consists of CE, RS, BL,
Reset, and CLK. The display pins are connected to the
corresponding bus line. Thus, all CE pins are connected to
the CE bus line. Similarly, bus lines for RS, BL, Reset, and
CLK are created. Then D_IN is connected to the right‑most
display. D_OUT from this display is connected to the next
display. The left‑most display receives its D_IN from the
D_OUT of the display to its right. D_OUT from the left‑most
display is not used.
Each display may be set to use its internal oscillator, or
the displays may be synchronized by setting up one
display as the master and the others as slaves. The slaves
are set to receive their oscillator input from the master’s
oscillator output.
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