HCMS-2975_13 Datasheet, PDF (7/16 Pages) AVAGO TECHNOLOGIES LIMITED – High Performance CMOS 5 x 7 Alphanumeric Displays

AC Timing Characteristics Over Temperature Range (-40°C to +85°C)
Timing
Diagram Ref.
Number
Description  Symbol
4.5 V < V_LOGIC <5.5 V
Min.
Max.
V_LOGIC = 3 V
Min. Max. Units
1
Register Select Setup Time to Chip Enable   t_rss
10
10
ns
2
Register Select Hold Time to Chip Enable
  t_rsh
10
10
ns
3
Rising Clock Edge to Falling
Chip Enable Edge
  t_clkce 20
20
ns 
4
Chip Enable Setup Time to Rising Clock Edge   t_ces
35
55
ns
5
Chip Enable Hold Time to Rising Clock Edge   t_ceh 20
20
ns
6
Data Setup Time to Rising Clock Edge
  t_ds
10
10
ns
7
Data Hold Time after Rising Clock Edge
  t_dh
10
10
ns
8
Rising Clock Edge to D_OUT[1]
  t_dout 10
40
10 65 ns
9
Propagation Delay D_IN to D_OUT
Simultaneous Mode for One IC^[1,2]
  t_doutp
18
30 ns 
10
CE Falling Edge to D_OUT Valid
11
Clock High Time
  t_cedo
25
45 ns
  t_clkh 80
100
ns
12
Clock Low Time
Reset Low Time
  t_clkl
  t_rstl
80
50
100
ns
50
ns
Clock Frequency
Internal Display Oscillator Frequency
  F_cyc
  F_inosc 80
5
210
80
4
MHz
210 KHz
Internal Refresh Frequency
External Display OscillatorFrequency
  F_rf
150
410
150 400 Hz
  F_exosc
  Prescaler = 1
51.2
1000
51.2 1000 KHz
  Prescaler = 8
410
8000
410 8000 KHz
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.