HCMS-3901 Datasheet, PDF (7/18 Pages) AVAGO TECHNOLOGIES LIMITED – 3.3 V High Performance CMOS 5x7 AlphaNumeric Displays

AC Timing Characteristics over Temperature Range (-40 to +85°C)
Timing
Diagram
Ref. Number
1
2
3
4
5
6
7
8
9
10
11
12
Description
Register Select Setup Time to Chip Enable
Register Select Hold Time to Chip Enable
Rising Clock Edge to Falling Chip Enable Edge
Chip Enable Setup Time to Rising Clock Edge
Chip Enable Hold Time to Rising Clock Edge
Data Setup Time to Rising Clock Edge
Data Hold Time after Rising Clock Edge
Rising Clock Edge to D_OUT ^[1]
Propagation Delay D_IN to D_OUT
Simultaneous Mode for one IC^[1,2]
CE Falling Edge to D_OUT Valid
Clock High Time
Clock Low Time
Reset Low Time
Clock Frequency
Internal Display Oscillator Frequency
Internal Refresh Frequency
External Display Oscillator Frequency
Prescaler = 1
Prescaler = 8
Symbol
t_rss
t_rsh
t_clkce
t_ces
t_ceh
t_ds
t_dh
t_dout
t_doutp
t_cedo
t_clkh
t_clkl
t_rstl
F_cyc
F_inosc
F_rf
F_exosc
4.5 V<V_LOGIC < 5.5 V
Min. Max.
10
10
20
35
20
10
10
10 40
18
25
80
80
50
5
80 210
150 410
51.2 1000
410 8000
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
V_LOGIC = 3 V
Min. Max. Units
10
ns
10
ns
20
ns
55
ns
20
ns
10
ns
10
ns
10 65 ns
30 ns
45 ns
100
ns
100
ns
50
ns
4
MHz
80 210 KHz
150 410 Hz
51.2 1000 KHz
410 8000 KHz
7