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HCPL-4504-500E Datasheet, PDF (13/19 Pages) AVAGO TECHNOLOGIES LIMITED – High CMR, High Speed Optocouplers | |||
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Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise speciï¬ed.
Parameter
Symbol Device
Min. Typ.* Max. Units Test Conditions
Input-Output
Momentary
Withstand
Voltageâ
VISO
HCPL-4504 3750
HCPL-0454
HCPL-J454 3750
V rms
RH â¤50%,
t = 1 min.,
TA = 25°C
HCPL-4504
Option 020
HCNW4504
5000
5000
Input-Output
RI-O
HCPL-4504
1012
Resistance
HCPL-0454
HCPL-J454
Ω
VI-O = 500 Vdc
HCNW4504 1012 1013
1011
Capacitance
CI-O
HCPL-4504
0.6
(Input-Output)
HCPL-0454
TA = 25°C
TA = 100°C
pF
f = 1 MHz
HCPL-J454
0.8
HCNW4504
0.5
0.6
Figure
Note
6, 13,
16
6, 14,
16
6, 11,
15
6, 15,
16
6
6
All typicals at TA = 25°C..
â The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety speciï¬cation or Avago Application Note 1074 entitled âOptocoupler Input-Output Endurance Voltage.â
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is deï¬ned as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on
the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e.,VO > 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse
signal, VCM, to assure that the output will remain in a Logic Low state (i.e.,VO < 1.0V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 μF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage â¥4500 V rms for 1 second (leakage detection
current limit, Ii-o â¤5 μA).
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage â¥4500 V rms for 1 second (leakage detection
current limit, Ii-o ⤠5 μA).
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage â¥6000 V rms for 1 second (leakage detection
current limit, Ii-o â¤5 μA).
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
17. The diï¬erence between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power Inverter Dead
Time and Propagation Delay Speciï¬cations section.)
13
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