HCPL-2503-000E Datasheet, PDF (12/12 Pages) AVAGO TECHNOLOGIES LIMITED – Single Channel, High Speed Logic Interface Optocoupler

Recommended Circuit Design Parameters
Parameter
Symbol
LSTTL-to-
LSTTL
Input
Logic Low Output
Voltage – Input Gate
V_OL (A) 0.5
Supply Voltage – Input
V_CC1
5.0
Input Resistor
R_IN
360
430
Input Current
I_F
8
Input Current Range
I_F
6.75–10
Output
Logic Low Output
Voltage – HCPL-2503
V_OL (B) 0.5
Supply Voltage – Output V_CC2
5.0
Pull-Up Resistor
R_L
20
Required Current Sink
for Logic Low
I_OL
0.61
(max)
HCPL-2503 Current
Transfer Ratio
CTR
11
Logic Low Output
Current – HCPL-2503
I_OL
0.74
(min)
Data Rate
f_D
250
TTL-to-
LSTTL Units
Comments
Fig. Note
0.4
V
Maximum
5.0
V
± 5%
180
Ω
± 5%
8a
200
8b
16
mA
Nominal
14.0–20 mA
8a
14.5–20
8b
0.5
V
Maximum
5.0
V
± 5%
8.2
kΩ
± 5%
11
1.0
mA
Worst Case V_CC,
12
R_L, I_IL (B)
9
%
Minimum T_A = 0˚C to
+70°C
1.26
mA
1.30
Worst Case V_CC, CTR, I_F
T_A = 0_°C to +70_°C
8a 13
8b
250
kb/s
NRZ, T_A = 25°C
14
Notes:
10. The inverting circuit has higher power consumption and must use open collector gates on the input.
11. The load resistor R_L must be large enough to guarantee logic LOW and small enough to guarantee logic HIGH under worst case conditions:
V_CC (max) – V_OL
I_OL (2503) – I_IL (B)
≤ R_L ≤
V_CC (min) – V_IH (B)
I_OH (2503) – I_IH (B)
The selection of R_L is the same for both inverting and non-inverting circuits.
12. The maximum current sink required for logic LOW is:
I_OL (max) = I_IL (B) (max) + I_R (max)
where I_R is the current through R_L.
13. The ratio of I_OL (min) to I_OL (max) gives the design margin for CTR degradation. See Application Note 1002.
14. The maximum data rate is defined as:
     f_D =   t_P   _H^  _L1 +t_{P L} _H        bits/second NRZ
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.
AV02-0520EN - June 15, 2007