HCPL-643X Datasheet, PDF (11/12 Pages) AVAGO TECHNOLOGIES LIMITED – Hermetically Sealed, Very High Speed, Logic Gate Optocouplers High radiation immunity

MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in compli-
ance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DLA drawings
5962-89570, and 5962-89571.
Testing consists of 100% screening and quality confor-
mance inspection to MIL-PRF-38534.
Data Rate and Pulse-Width Distortion Definitions
Propagation delay is a figure of merit which describes the
finite amount of time required for a system to translate in-
formation from input to output when shifting logic levels.
Propagation delay from low to high (t_PLH) specifies the
amount of time required for a system’s output to change
from a Logic 0 to a Logic 1, when given a stimulus at the
input. Propagation delay from high to low (t_PHL) specifies
the amount of time required for a system’s output to
change from a Logic 1 to a Logic 0, when given a stimulus
at the input (see Figure 5).
When t_PLH and t_PHL differ in value, pulse width distortion
results. Pulse width distortion is defined as |t_PHL - t_PLH| and
determines the maximum data rate capability of a dis-
tortion-limited system. Maximum pulse width distortion
on the order of 25-35% is typically used when specifying
the maximum data rate capabilities of systems. The exact
figure depends on the particular application (RS-232,
PCM, T-1, etc.).
These high performance optocouplers offer the advan-
tages of specified propagation delay (t_PLH, t_PHL), and pulse
width distortion (|t_PLH -t _PHL|) over temperature and power
supply voltage ranges.
Applications
VCC1 = +5 V
226 Ω ^{30 pF}
DATA
IN
A
274 Ω
HCPL-5400
VCC
GND 1
1
TOTEM
POLE
OUTPUT GATE
(e.g. 54AS1000)
GND
Y=A
Figure 13. Recommended HCPL-5400 interface circuit
V_CC2 = 5 V
0.1 μF
TTL
LSTTL
STTL
HCMOS
DATA
OUT
Y
GND 2
2
VCC1 = +5 V
DATA
IN
A
STTL
464 Ω
HCPL-5400
VCC
GND 1
1
OPEN
COLLECTOR
OUTPUT
GATE
(e.g. 54S05)
GND
Y=A
Figure 14. Alternative HCPL-5400 interface circuit
0.1 μF
TTL
LSTTL
STTL
VCC2 = 5 V
DATA
OUT
Y
GND 2
2
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