ATTINY25_07 Datasheet, PDF (98/201 Pages) ATMEL Corporation – 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

15.2.9
Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A -
OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the
PB1(OC1A).
When the counter value match the content of OCR1A, the OC1A and output is set or cleared
according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as
shown in Table 15-3.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will
set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Table 15-3.
COM1A1
0
0
1
1
Compare Mode Select in PWM Mode
COM1A0 Effect on Output Compare Pin
0
OC1A not connected.
1
OC1A not connected.
0
OC1A cleared on compare match. Set when TCNT1 = $01.
1
OC1A set on compare match. Cleared when TCNT1 = $01.
Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first
transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter
reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event
of an unsynchronized OCR1A. See Figure 15-4 for an e xample.
Figure 15-4. Effects of Unsynchronized OCR Latching
Compare Value changes
Counter Value
Compare Value
Synchronized OC1A Latch
PWM Output OC1A
Compare Value changes
Counter Value
Compare Value
Unsynchronized OC1A Latch
Glitch
PWM Output OC1A
During the time between the write and the latch operation, a read from OCR1A will read the con-
tents of the temporary location. This means that the most recently written value always will read
out of OCR1A.
98 ATtiny25/45/85 Auto
7598D–AVR–02/07