ATTINY25_07 Datasheet, PDF (101/201 Pages) ATMEL Corporation – 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

ATtiny25/45/85 Auto
The dead time generation is based on the 4-bit down counters that count the dead time, as
shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can
divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of
dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10
from the I/O register at address 0x23. The block has also a rising and falling edge detector that
is used to start the dead time counting period. Depending on the edge, one of the transitions on
the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The compara-
tor is used to compare the counter with zero and stop the dead time insertion when zero has
been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register,
depending on the edge of the PWM generator output when the dead time insertion is started.
Figure 16-2. Dead Time Generator
T/C1 CLOCK DTPS11..10
COMPARATOR
OC1x
DEAD TIME
PRESCALER
CLOCK CONTROL
4-BIT COUNTER
OC1x
DT1x
I/O REGISTER
PWM1x
The length of the counting period is user adjustable by selecting the dead time prescaler setting
in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
Figure 16-3. The Complementary Output Pair
PWM1x
OC1x
OC1x
x = A or B
t _{non-overlap / rising edge} t _{non-overlap / falling edge}
16.0.1 Timer/Counter1 Dead Time Prescaler register 1 - DTPS1
Bit
7
6
5
4
3
2
1
0
$23 ($43)
DTPS11 DTPS10 DTPS1
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
7598D–AVR–02/07
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