AT94K Datasheet, PDF (98/192 Pages) ATMEL Corporation – 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE

• Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits
These bits select PWM operation of Timer/Counter1 as specified in Table 27. This mode is
described on page 101.
Table 27. PWM Mode Select
PWM11
PWM10 Description
0
0
PWM operation of Timer/Counter1 is disabled
0
1
Timer/Counter1 is an 8-bit PWM
1
0
Timer/Counter1 is a 9-bit PWM
1
1
Timer/Counter1 is a 10-bit PWM
Timer/Counter1 Control Register B – TCCR1B
Bit
$2E ($4E)
Read/Write
Initial Value
7
6
5
4
ICNC1 ICES1 ICPE
-
R/W
R/W
R/W
R
0
0
0
0
3
CTC1
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
• Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis-
abled. The input capture is triggered at the first rising/falling edge sampled on the PE7(ICP) –
input capture pin – as specified. When the ICNC1 bit is set (one), four successive samples are
measures on the PE7(ICP) – input capture pin, and all samples must be High/Low according
to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is
XTAL clock frequency.
• Bit 6 - ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input
Capture Register – ICR1 – on the falling edge of the input capture pin – PE7(ICP). While the
ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Reg-
ister – ICR1 – on the rising edge of the input capture pin – PE7(ICP).
• Bit 5 - ICPE: Input Captive Pin Enable
This bit must be set by the user to enable the Input Capture Function of timer1. Disabling pre-
vents unnecessary register copies during normal use of the PE7 port.
• Bit 4 - Res: Reserved Bit
This bit is reserved in the FPSLIC and will always read zero.
• Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle
after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting
and is unaffected by a compare match. When a prescaling of 1 is used, and the compareA
register is set to C, the timer will count as follows if CTC1 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the
Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter
wraps when it reaches the TOP value. Refer to page 101 for a detailed description.
98 AT94K Series FPSLIC
Rev. 1138F–FPSLI–06/02