AT94K Datasheet, PDF (97/192 Pages) ATMEL Corporation – 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE

AT94K Series FPSLIC
Timer/Counter1 Control Register A – TCCR1A
Bit
$2F ($4F)
Read/Write
Initial Value
7
COM1A1
R/W
0
6
COM1A0
R/W
0
5
COM1B1
R/W
0
4
COM1B0
R/W
0
3
FOC1A
R/w
0
2
FOC1B
R/W
0
1
PWM11
R/W
0
0
PWM10
R/W
0
TCCR1A
• Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare
match in Timer/Counter1. Any output pin actions affect pin OC1A – Output CompareA pin
PE6. This is an alternative function to an I/O port, and the corresponding direction control bit
must be set (one) to control an output pin. The control configuration is shown in Table 26.
• Bits 5,4 - COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a compare
match in Timer/Counter1. Any output pin actions affect pin OC1B – Output CompareB pin
PE5. This is an alternative function to an I/O port, and the corresponding direction control bit
must be set (one) to control an output pin. The following control configuration is given:
Table 26. Compare 1 Mode Select⁽¹⁾
COM1X1⁽²⁾ COM1X0⁽²⁾ Description
0
0
Timer/Counter1 disconnected from output pin OC1X
0
1
Toggles the OC1X output line
1
0
Clears the OC1X output line (to zero)
1
1
Sets the OC1X output line (to one)
Notes: 1. In PWM mode, these bits have a different function. Refer to Table 30 for a detailed
description.
2. X = A or B
• Bit 3 - FOC1A: Force Output Compare1A
Writing a logic 1 to this bit forces a change in the compare match output pin PE6 according to
the values already set in COM1A1 and COM1A0. If the COM1A1 and COM1A0 bits are written
in the same cycle as FOC1A, the new settings will not take effect until next compare match or
forced compare match occurs. The Force Output Compare bit can be used to change the out-
put pin without waiting for a compare match in the timer. The automatic action programmed in
COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is gen-
erated and it will not clear the timer even if CTC1 in TCCR1B is set. The FOC1A bit will always
be read as zero. The setting of the FOC1A bit has no effect in PWM mode.
• Bit 2 - FOC1B: Force Output Compare1B
Writing a logic 1 to this bit forces a change in the compare match output pin PE5 according to
the values already set in COM1B1 and COM1B0. If the COM1B1 and COM1B0 bits are written
in the same cycle as FOC1B, the new settings will not take effect until next compare match or
forced compare match occurs. The Force Output Compare bit can be used to change the out-
put pin without waiting for a compare match in the timer. The automatic action programmed in
COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is gen-
erated. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect
in PWM mode.
97
Rev. 1138F–FPSLI–06/02