AT94K Datasheet, PDF (106/192 Pages) ATMEL Corporation – 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE

Multiplier
The multiplier is capable of multiplying two 8-bit numbers, giving a 16-bit result using only two
clock cycles. The multiplier can handle both signed and unsigned integer and fractional num-
bers without speed or code size penalty. Below are some examples of using the multiplier for
8-bit arithmetic.
To be able to use the multiplier, six new instructions are added to the AVR instruction set.
These are:
• MUL, multiplication of unsigned integers
• MULS, multiplication of signed integers
• MULSU, multiplication of a signed integer with an unsigned integer
• FMUL, multiplication of unsigned fractional numbers
• FMULS, multiplication of signed fractional numbers
• FMULSU, multiplication of a signed fractional number and with an unsigned fractional
number
The MULSU and FMULSU instructions are included to improve the speed and code density for
multiplication of 16-bit operands. The second section will show examples of how to efficiently
use the multiplier for 16-bit arithmetic.
The component that makes a dedicated digital signal processor (DSP) specially suitable for
signal processing is the multiply-accumulate (MAC) unit. This unit is functionally equivalent to
a multiplier directly connected to an arithmetic logic unit (ALU). The FPSLIC-based AVR Core
is designed to give FPSLIC the ability to effectively perform the same multiply-accumulate
operation.
The multiply-accumulate operation (sometimes referred to as multiply-add operation) has one
critical drawback. When adding multiple values to one result variable, even when adding posi-
tive and negative values to some extent, cancel each other; the risk of the result variable to
overrun its limits becomes evident, i.e. if adding 1 to a signed byte variable that contains the
value +127, the result will be -128 instead of +128. One solution often used to solve this prob-
lem is to introduce fractional numbers, i.e. numbers that are less than 1 and greater than or
equal to -1. Some issues regarding the use of fractional numbers are discussed.
A list of all implementations with key performance specifications is given in Table 33.
Table 33. Performance Summary
8-bit x 8-bit Routines:
Unsigned Multiply 8 x 8 = 16 bits
Signed Multiply 8 x 8 = 16 bits
Fractional Signed/Unsigned Multiply 8 x 8 = 16 bits
Fractional Signed Multiply-accumulate 8 x 8 + = 16 bits
16-bit x 16-bit Routines:
Signed/Unsigned Multiply 16 x 16 = 32 bits
UnSigned Multiply 16 x 16 = 32 bits
Signed Multiply 16 x 16 = 32 bits
Signed Multiply-accumulate 16 x 16 + = 32 bits
Fractional Signed Multiply 16 x 16 = 32 bits
Fractional Signed Multiply-accumulate 16 x 16 + = 32 bits
Word (Cycles)
1 (2)
1 (2)
1 (2)
3 (4)
Word (Cycles)
6 (9)
13 (17)
15 (19)
19 (23)
16 (20)
21 (25)
106 AT94K Series FPSLIC
Rev. 1138F–FPSLI–06/02