AT90PWM161_14 Datasheet, PDF (95/327 Pages) ATMEL Corporation – 131 powerful instructions - most single clock cycle execution

AT90PWM81/161
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt must be used to extend the resolution
for the capture unit.
11.6.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13 = 1, previous mode 12), the ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches the ICR1 . The ICR1 define the top value for the counter,
hence also its resolution. This mode allows greater control of the compare match output fre-
quency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 11-5. The counter value (TCNT1)
increases until a compare match occurs with ICR1, and then counter (TCNT1) is cleared.
Figure 11-5. CTC mode, timing diagram.
ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
An interrupt can be generated at each time the counter value reaches the TOP value by using
the ICF1 Flag . If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is
running with none or a low prescaler value must be done with care since the CTC mode does
not have the double buffering feature. If the new value written to ICR1 is lower than the current
value of TCNT1, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. In many cases this feature is not desirable.
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
11.7
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
Figure 11-6 on page 96 shows the count sequence close to TOP in various modes.
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