AT90PWM161_14 Datasheet, PDF (166/327 Pages) ATMEL Corporation – 131 powerful instructions - most single clock cycle execution

AT90PWM81/161
13.16 PSCR Input Mode 8: Edge Retrigger PSC
Figure 13-26. PSCR behavior versus PSCr Input A in Mode 8.
DT0 OT0
DT1 OT1
DT0 OT0
DT1 OT1
PSCOUTn0
PSCOUTn1
DT0 OT0
DT1 OT1
PSCn Input A
The output frequency is modulated by the occurrence of significative edge of retriggering input.
Figure 13-27. PSCR behavior versus PSCr Input B in Mode 8.
DT0 OT0
DT0 OT0
DT1 OT1
DT1 OT1
DT0 OT0
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input B
or
PSCn Input B
The output frequency is modulated by the occurrence of significative edge of retriggering input.
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSCR
doesn’t jump to the opposite dead-time.
7734Q–AVR–02/12
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