ATTINY43U_1 Datasheet, PDF (90/182 Pages) ATMEL Corporation – 8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter

Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
TOP
BOTTOM
BOTTOM + 1
OCFnx
12.9 Register Description
12.9.1 TCCR0A – Timer/Counter Control Register A
Bit
7
6
5
4
3
0x30 (0x50)
COM0A1 COM0A0 COM0B1 COM0B0
–
Read/Write
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
2
1
0
–
WGM01 WGM00 TCCR0A
R
R/W
R/W
0
0
0
12.9.2
TCCR1A – Timer/Counter Control Register A
Bit
7
6
5
4
3
0x2F (0x4F)
COM1A1 COM1A0 COM1B1 COM1B0
–
Read/Write
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
2
1
0
–
WGM11 WGM10 TCCR1A
R
R/W
R/W
0
0
0
• Bits 7:6 – COMnA[1:0]: Compare Match Output A Mode
These bits control the Output Compare pin (OCnA) behavior. If one or both of the COMnA[1:0]
bits are set, the OCnA output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA pin
must be set in order to enable the output driver.
When OCnA is connected to the pin, the function of the COMnA[1:0] bits depends on the
WGMn[2:0] bit setting. Table 12-2 on page 90 shows the COMnA[1:0] bit functionality when the
WGMn[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 12-2.
COMnA1
0
0
1
1
Compare Output Mode, non-PWM Mode
COMnA0 Description
0
Normal port operation, OCnA disconnected.
1
Toggle OCnA on Compare Match
0
Clear OCnA on Compare Match
1
Set OCnA on Compare Match
90 ATtiny43U
8048B–AVR–03/09