ATTINY43U_1 Datasheet, PDF (129/182 Pages) ATMEL Corporation – 8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter

When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
page 125.
16.13.4 ADCSRB – ADC Control and Status Register B
Bit
0x03 (0x23)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
BS
ACME
–
ADLAR
–
ADTS2 ADTS1 ADTS0 ADCSRB
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
• Bit 5 – Res: Reserved Bit
This bit is reserved and will always read what was written.
• Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see “ADCL and ADCH – ADC Data Register” on
page 128.
• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read what was written.
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 16-6. ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
8048B–AVR–03/09
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