ATTINY43U_1 Datasheet, PDF (12/182 Pages) ATMEL Corporation – 8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter

4.6.1 SPH and SPL — Stack Pointer Register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Read/Write
Initial Value
Initial Value
15
SP15
SP7
7
R/W
R/W
RAMEND
RAMEND
14
SP14
SP6
6
R/W
R/W
RAMEND
RAMEND
13
SP13
SP5
5
R/W
R/W
RAMEND
RAMEND
12
SP12
SP4
4
R/W
R/W
RAMEND
RAMEND
11
SP11
SP3
3
R/W
R/W
RAMEND
RAMEND
10
SP10
SP2
2
R/W
R/W
RAMEND
RAMEND
9
SP9
SP1
1
R/W
R/W
RAMEND
RAMEND
8
SP8
SP0
0
R/W
R/W
RAMEND
RAMEND
SPH
SPL
4.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clk_CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 4-5. Single Cycle ALU Operation
T1
T2
T3
T4
clk_CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
12 ATtiny43U
8048B–AVR–03/09