U2731B Datasheet, PDF (9/25 Pages) ATMEL Corporation – DAB ONE- CHIP FRONT END

U2731B
If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the refer-
ence divider has to be specified in such a way that the division process results in an
output frequency which is four times higher than the desired frequency raster, i.e., the
comparison frequency of the phase detector equals four times the frequency raster. By
changing the division ratio of the main divider from N to N+1 in an appropriate way
(fractional-N technique), this frequency raster is interpolated to deliver a frequency
spacing of 16 kHz. So effectively a reference scaling divide factor
∑ ^SFref,eff ^{= 4 × r}i ^{× 2i is achieved.}
By setting, the two-wire bus bit T, a test signal representing the divided input signal can
be monitored at the switching output SWA.
Main Divider
Phase Comparator and
Charge Pump
The main divider consists of a fully programmable 13-bit divider which defines a division
ratio N. The applied division ratio is either N or N+1 according to the control of a special
control unit. On average, the scaling factors SF = N + k/4 can be selected where k = 0,
1, 2 or 3.
In this way, VCO frequencies f_VCO = 4 × (N+k/4) × f_ref/(4 × SF_ref) can be synthesized
starting from a reference frequency fref. If we define SF_eff = 4 × N + k and
SF_ref,eff = 4 × SF_ref (previous section), then f_VCO = SF_eff × f_ref/SF_ref,eff, where SF_eff is
defined by 15 bits.
In the following, this circuit is described in terms of SF_eff and SF_ref,eff. SF_eff has to be pro-
grammed via the two-wire bus interface. An effective scaling factor from 2048 to 32767
can be selected by means of the two-wire bus bits ni (i = 0, ..., 14) according to
∑ ^SFeff ^{= n}i ^{× 2i}
By setting the two-wire bus bit T, a test signal representing the divided input signal can
be monitored at the switching output SWC.
When the supply voltage is switched on, both the reference divider and the programma-
ble divider are kept in RESET state until a complete scaling factor is written onto the
chip. Changes in the setting of the programmable divider become active when the corre-
sponding two-wire bus transmission is completed. An internal synchronization
procedure ensures that such changes do not become active while the charge pump is
sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the
output frequency without restricting the controlled VCO's frequency spectrum.
The tri-state phase detector causes the charge pump to source or to sink current at the
output Pin PD depending on the phase relation of its input signals which are provided by
the reference and the main divider respectively. Four different values of this current can
be selected by means of the two-wire bus bits I50 and I100. By use of this option,
changes of the loop characteristics due to the variation of the VCO gain as a function of
the tuning voltage can be reduced. The charge-pump current can be switched off using
the two-wire bus bit TRI. A change in the setting of the charge pump current becomes
active when the corresponding two-wire bus transmission is completed. As described for
the setting of the scaling factor of the programmable divider, an internal synchronization
procedure ensures that such changes do not become active while the charge pump is
sourcing or sinking current at its output pin. This behavior allows a change in the charge
pump current without restricting the controlled VCO's frequency spectrum.
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4671C–DAB–06/04