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U2731B Datasheet, PDF (18/25 Pages) ATMEL Corporation – DAB ONE- CHIP FRONT END
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min. Typ. Max. Unit Type*
10 Phase Detector
39
10.1
I100 = HIGH, I50 = HIGH
10.2
I100 = HIGH, I50 = LOW
Charge-pump current
10.3
I100 = LOW, I50 = HIGH
10.4
I100 = LOW, I50 = LOW
10.5 High impedance mode TRI = HIGH
10.6 Effective phase noise(1) IPD = 203 mA
IPD4
IPD3
IPD2
IPD1
IPD,tri
LPD
160 200 240 µA
A
120 150 180 µA
A
80 100 120 µA
A
35 50
65
µA
A
-100
100 nA
A
-159
dBc/
Hz
C
11 Lock Indication
41
11.1 Leakage current
11.2 Saturation voltage
12 Switches
VPLCK = 5.5 V
IPLCK = 0.25 mA
3, 4, 6
IPLCK,L
VPLCK,sat
10
µA
A
0.5
V
A
12.1 Leakage current
12.2 Saturation voltage
13 Address Selection
ISW = 0.25 mA
ISW,L
VSW,sat
44
10
µA
A
0.5
V
A
13.1 AS1 = 0
13.2 AS1 = 1
14 D/A Converters
7, 8, 9
0
0.1 VS
C
0.4
VS
0.6 VS
C
14.1 Output voltage
Cα7 = HIGH
Cα0 to Cα6 = LOW
α = A, B, C
VM
4.05 4.25 4.45 V
A
14.2 Variation of VM
14.3 Variation of VM
14.4 Accuracy
VS = 8.00 to 9.35 V
Tamb = -40 to +85° C
VCαn-n VM/128
n = 24 ... 232, α = A, B, C
∆VM,VS
-50
50 mV
A
∆VM,temp
±20
mV
C
∆VCαn
-70
70 mV
A
14.5
Maximum output
current
15 Simple Two-wire Bus
ICAOmax
ICBOmax
20
µA
C
ICCOmax
1, 2
15.1 Input voltage SCL/SDA HIGH
3
5.5
V
D
15.2 Input voltage SCL/SDA LOW
1.5
V
D
15.3
Output voltage SDA
(open collector)
ISDA = 2 mA,
SDA = LOW
0.4
V
D
15.4 SCL clock frequency
0.1
100 kHz
D
15.5 Rise time (SCL, SDA)
15.6 Fall time (SCL; SDA)
15.7
Time before new
transmission can start
tr
tf
tbuf
4.7
1
µs
D
300 µs
D
µs
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency
of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
18 U2731B
4671C–DAB–06/04