U2731B Datasheet, PDF (7/25 Pages) ATMEL Corporation – DAB ONE- CHIP FRONT END

U2731B
IF Part
IF Gain-controlled
Amplifier
The signal applied to the balanced input pins IFIN1, IFIN2 is amplified by a gain-con-
trolled IF amplifier. The gain-control signal is generated by an IF AGC voltage-
generation block which is described in the next section. To avoid offset problems, the
output of the gain-controlled amplifier is fed to an amplifier/mixer combination by AC
coupling.
IF Gain-controlled
Amplifier/Mixer
Combination
Depending on the setting of the two-wire bus bits M2, M3, the output signal of the gain-
controlled IF amplifier is either mixed down to a lower, second IF or, after passing an
output buffer stage, amplified before it appears at the single-ended output pin IFOUT. If
the down-conversion option is chosen this circuit still offers two possibilities concerning
the synthesis of the IF mixers LO signal. This LO signal is derived from the PLL's on-
chip reference oscillator. By means of the two-wire bus bits M2, M3, it can be decided
whether the reference frequency is doubled before it is given to the mixer's LO port, or if
it is used directly. The gain-control voltage of the amplifier/mixer combination is similar
to the gain-controlled IF amplifier generated by an internal gain-control circuit.
IF AGC
Voltage-generation Block
The purpose of this gain-control circuit in the IF part is to measure the power of the
incoming signal at the balanced input pins IFAGCIN1, IFAGCIN2, to compare it with a
certain power level and to generate a control voltage for the IF gain-controlled amplifiers
and mixer. This architecture offers the possibility of ensuring an optimal use of the
dynamic range of the A/D converter which transforms the output signal at pin IFOUT
from the analog to the digital domain despite possible insertion losses of (anti-aliasing)
filters which are arranged in front of the converter. Such a constellation is indicated in
the application circuit in Figure 8 on page 20.
The incoming signal at the balanced input pins IFAGC1, IFAGC2 passes a power-mea-
surement process similar to that described in the section “RF AGC Voltage-generation
Block” on page 6. For flexibility reasons, no bandpass filtering is implemented. The volt-
age derived in this process is compared to a voltage threshold (th3) which is defined by
an on-chip 4-bit D/A converter. The setting of this converter is defined by the two-wire
bus bits TCi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump
feeds a positive or negative current to pin CPIF in order to charge or discharge an exter-
nal capacitor. By means of the pins WAGC and SLI the current of this charge pump can
be selected according to the following table:
Table 2. Current of Charge Pump
WAGC
SLI
HIGH
X
LOW
LOW
LOW
HIGH
Charge-pump Current/µA
off
50 µA (slow mode)
190 µA (fast mode)
The function can be seen in Figure 12 on page 23.
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4671C–DAB–06/04