ATR0621 Datasheet, PDF (9/20 Pages) ATMEL Corporation – GPS Baseband Processor

Table 3-2.
Module
SPI
WD
PIO
GPS
JTAG/ICE
CLOCK
RESET
POWER
LDOBAT
LDO18
ATR0621 Signal Description (Continued)
Name
Function
SCK
SPI Clock
MOSI
Master Out Slave In
MISO
Master In Slave Out
NSS/NPCS0 Slave Select
NPCS1-3
Slave Select
NWD_OVF
Watchdog Timer Overflow
P0-31
Programmable I/O Port
GPSMODE0-12 GPS Mode
SIGHI1
Digital IF
SIGLO1
Digital IF
SIGHI2
Digital IF
SIGLO2
Digital IF
TIMEPULSE GPS synchronized time pulse
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
TCK
Test Clock
NTRST
Test Reset Input
DBG_EN
Debug Enable
CLK23
Clock Input
MCLK_OUT
Master Clock Output
NRESET
Reset Input
VDD18
VBAT18
VDDIO
VDD_USB
GND
LDOBAT_IN
VBAT
VBAT18
LDO_IN
LDO_OUT
LDO_EN
LDO In
LDO Out
LDO Enable
ATR0621 [Preliminary]
Type
I/O
I/O
I/O
I/O
Output
Output
I/O
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Input
Input
Output
I/O
Power
Power
Power
Power
Power
Power
Power
Out
Power
Power
Input
Active Level Comment
–
PIO-controlled after reset
–
PIO-controlled after reset
–
PIO-controlled after reset
Low PIO-controlled after reset
Low PIO-controlled after reset
–
PIO-controlled after reset
–
Input after reset
–
PIO-controlled after reset
–
Interface to ATR0600
–
Interface to ATR0600
–
PIO-controlled after reset
–
PIO-controlled after reset
–
PIO-controlled after reset
–
Internal pull-up resistor
–
Internal pull-up resistor
–
–
Internal pull-up resistor
Low Internal pull-down resistor
–
Internal pull-down resistor
–
Interface to ATR0600, Schmitt
trigger input
–
PIO-controlled after reset
Low
Open drain with internal pull-up
resistor
–
Core voltage 1.8V
–
Backup power 1.8V
–
Variable I/O voltage
–
USB voltage 3.0V to 3.6V
–
Ground
–
1.8V to 3.6V
–
1.95V to 3.6V
–
1.8V backup voltage
–
1.65V to 3.6V
–
1.8V core voltage, max. 100 mA
–
9
4890AS–GPS–09/05