AT17C020 Datasheet, PDF (9/12 Pages) ATMEL Corporation – 2-megabit FPGA Configuration EEPROM Memory

AT17C/LV020
AC Characteristics for AT17LV020
V_CC = 3.3V ± 10%
Commercial
Industrial/Military⁽¹⁾
Symbol Description
Min
Max
Min
Max
T_OE(2)
T_CE(2)
T_CAC(2)
OE to Data Delay
CE to Data Delay
CLK to Data Delay
5.00
55.0
55.0
60.0
55.0
60.0
T_OH
T_DF(3)
Data Hold From CE, OE or CLK
CE or OE to Data Float Delay
0.0
0.0
50.0
50.0
T_LC
CLK Low Time
25.0
25.0
T_HC
CLK High Time
25.0
25.0
T_SCE
CE Setup Time to CLK (to guarantee proper counting)
30.0
35.0
T_HCE
CE Hold Time from CLK (to guarantee proper counting)
0.0
0.0
T_HOE
OE High Time (guarantees counter is reset)
25.0
25.0
F_MAX
Notes:
MAX Input Clock Frequency
12.5
7.5
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
AC Characteristics for AT17LV020 When Cascading
V_CC = 3.3V ± 10%
Commercial
Industrial/Military⁽¹⁾
Symbol Description
Min
Max
Min
Max
T_CDF(3) CLK to Data Float Delay
50.0
50.0
T_OCK(2)
T_OCE(2)
CLK to CEO Delay
CE to CEO Delay
50.0
55.0
40.0
80.0
T_OOE(2) RESET/OE to CEO Delay
35.0
35.0
F_MAX
Notes:
MAX Input Clock Frequency
12.5
7.5
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
Units
ns
ns
ns
ns
MHz
9