AT91SAM7A3_04 Datasheet, PDF (88/575 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

I/O Lines Description
Table 16. I/O Lines Description
Name
FWKUP
WKUP0
WKUP1
SHDW
Description
Force Wake Up input for the Shutdown Controller
Wake-up 0 input
Wake-up 1input
Shutdown output
Type
Input
Input
Input
Output
Product
Dependencies
Power
Management
The Shutdown Controller is continuously clocked by Slow Clock. The Power Management
Controller has no effect on the behavior of the Shutdown Controller.
Functional
Description
The Shutdown Controller manages the main power supply. To do so, it is supplied with
VDDBU and manages wake-up input pins and one output pin, SHDW.
A typical application connects the pin SHDW to the shutdown input of the DC/DC Converter
providing the main power supplies of the system, and especially VDDCORE and/or VDDIO.
The wake-up inputs (WKUP0, WKUP1, FWKUP) connect to any push-buttons or signal that
wake up the system.
The software is able to control the pin SHDW by writing the Shutdown Control Register
(SHDW_CR) with the bit SHDW at 1. This register is password-protected and so the value
written should contain the correct key for the command to be taken into account. As a result,
the system should be powered down.
A level change on pins WKUP0 or WKUP1 is used as wake-up. Wake-up is configured in the
Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect
either a positive or negative transition or any level change on the pins WKUP0 and WKUP1.
The detection can also be disabled. Programming is performed by defining the fields
WKMODE0 and WKMODE1.
Moreover, a debouncing circuit can be programmed for the pin WKUP0 or WKUP1. The
debouncing circuit filters pulses on WKUP0 or WKUP1 shorter than the programmed number
of 16 SLCK cycles in CPTWK0 or CPTWK1 of the SHDW_MR register. If the programmed
level change is detected on a pin, a counter starts. When the counter reaches the value pro-
grammed in the corresponding field, CPTWK0 or CPTWK1, the SHDW pin is released. If a
new input change is detected before the counter reaches the corresponding value, the counter
is stopped and cleared. The field WAKEUP0 and/or WAKEUP1 of the Status Register
(SHDW_SR) reports the detection of the programmed events on WKUP0 or WKUP1. These
fields are reset after the read of SHDW_SR.
The pin FWKUP is treated differently and a low level on this pin forces a de-assertion of the
SHDW pin, regardless of the presence of the Slow Clock. The bit FWKUP in the status register
reports a Forced Wakeup Event after internal resynchronization of the event with the Slow
Clock.
88 AT91SAM7A3 Preliminary
6042A–ATARM–23-Dec-04