AT91SAM7A3_04 Datasheet, PDF (153/575 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7A3 Preliminary
Clock Generator
Description
Slow Clock RC
Oscillator
Main Oscillator
The Clock Generator is made up of one PLL, a Main Oscillator and an RC Oscillator. It pro-
vides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system.
• MAINCK is the output of the Main Oscillator
• PLLCK is the output of the Divider and PLL block
The Clock Generator User Interface is embedded within the Power Management Controller
User Interface and is described in “Power Management Controller (PMC) User Interface” on
page 165. However, the Clock Generator registers are named CKGR_.
The slow clock is the output of the RC Oscillator and is the only clock considered permanent in
a system that includes the Power Management Controller. It is mandatory in the operations of
the PMC.
The user has to take the possible drifts of the RC Oscillator into account. More details are
given in the DC Characteristics section of the product datasheet.
Figure 49 shows the Main Oscillator block diagram.
Figure 49. Main Oscillator Block Diagram
MOSCEN
XIN
XOUT
Main
Oscillator
MAINCK
Main Clock
Main Oscillator
Connections
SLCK
Slow Clock
OSCOUNT
Main
Oscillator
Counter
Main Clock
Frequency
Counter
MOSCS
MAINF
MAINRDY
The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz funda-
mental crystal. The typical crystal connection is illustrated in Figure 50. The 1 kΩ resistor is
only required for crystals with frequencies lower than 8 MHz. The oscillator contains 25 pF
capacitors on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a
crystal with a load capacitance of 12.5 pF is used. For further details on the electrical charac-
teristics of the Main Oscillator, see the DC Characteristics section of the product datasheet.
6042A–ATARM–23-Dec-04
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