AT91SAM7A3_04 Datasheet, PDF (384/575 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

PWM Channel
Block Diagram
Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by
DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode regis-
ter are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
Figure 100. Functional View of the Channel Block Diagram
inputs
from clock
generator
Channel
Clock
Selector
Internal
Counter
Comparator
inputs from
APB bus
PWMx
output waveform
Waveform Properties
Each of the 8 channels is composed of three blocks:
• A clock selector which selects one of the clocks provided by the clock generator described
in Section “PWM Clock Generator” on page 383.
• An internal counter clocked by the output of the clock selector. This internal counter is
incremented or decremented according to the channel configuration and comparators
events. The size of the internal counter is 20 bits.
• A comparator used to generate events according to the internal counter value. It also
computes the PWMx output waveform according to the configuration.
The different properties of output waveforms are:
• the internal clock selection. The internal channel counter is clocked by one of the clocks
provided by the clock generator described in the previous section. This channel parameter
is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.
• the waveform period. This channel parameter is defined in the CPRD field of the
PWM_CPRDx register.
If the waveform is left aligned then: period = 1/fchannel_x_clock * CPRD
If the waveform is center aligned then: period = 2/fchannel_x_clock * CPRD
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
PWM_CDTYx register.
If the waveform is left aligned then:
duty cycle = (period - 1/fchannel_x_clock * CDTY) / period
If the waveform is center aligned, then:
duty cycle = ((period / 2) - 1/fchannel_x_clock * CDTY)) / (period / 2)
• the waveform polarity. At the beginning of the period, the signal can be at high or low
level. This property is defined in the CPOL field of the PWM_CMRx register. By default the
signal starts by a low level.
384 AT91SAM7A3 Preliminary
6042A–ATARM–23-Dec-04