ATUC128L3U_14 Datasheet, PDF (856/963 Pages) ATMEL Corporation – High-performance, Low-power 32-bit Atmel

ATUC64/128/256L3/4U
34.4.3 Block Diagram
Figure 34-5. JTAG and Boundary-scan Access
32-bit AVR device
JTAG master
TMS TCK
TDO TDI
TMS TCK
TDO TDI
2nd JTAG
device
JTAG
TAP
Controller
Boundary scan enable
TCK
TMS
TDI
TDO
Instruction register
scan enable
Data register
scan enable
Instruction Register
JTAG data registers
Device Identification
Register
By-pass Register
Reset Register
Part specific registers
...
Service Access Bus
interface
Internal I/O
SAB
lines
34.4.4 I/O Lines Description
Table 34-7.
Pin Name
RESET_N
TCK
TMS
TDI
TDO
I/O Line Description
Pin Description
External reset pin. Used when enabling and disabling the JTAG.
Test Clock Input. Fully asynchronous to system clock frequency.
Test Mode Select, sampled on rising TCK.
Test Data In, sampled on rising TCK.
Test Data Out, driven on falling TCK.
Type
Input
Input
Input
Input
Output
Active Level
Low
34.4.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
32142D–06/2013
856