ATUC128L3U_14 Datasheet, PDF (256/963 Pages) ATMEL Corporation – High-performance, Low-power 32-bit Atmel

ATUC64/128/256L3/4U
14.5.7
System RC Oscillator (RCSYS)
Rev: 1.1.1.0
The system RC oscillator has a startup time of three cycles, and is always available except in
some sleep modes. Please refer to the Power Manager chapter for details. The system RC oscil-
lator operates at a nominal frequency of 115kHz, and is calibrated using the Calibration Value
field (CALIB) in the RC Oscillator Calibration Register (RCCR). After a Power-on Reset (POR),
the RCCR.CALIB field is loaded with a factory defined value stored in the Flash fuses. Please
refer to the Fuse setting chapter for more details about RCCR fuses and how to program the
fuses.
If the Flash Calibration Done (FCD) bit in the RCCR is zero at any reset, the flash calibration will
be redone and the RCCR.FCD bit will be set before program execution starts in the CPU. If the
RCCR.FCD is one, the flash calibration will only be redone after a Power-on Reset.
To prevent unexpected writes to RCCR due to software bugs, write access to this register is pro-
tected by a locking mechanism. For details please refer to the UNLOCK register description.
Although it is not recommended to override default factory settings, it is still possible to override
the default values by writing to RCCR.CALIB.
14.5.8
Voltage Regulator (VREG)
Rev: 1.1.0.0
The embedded voltage regulator can be used to provide the VDDCORE voltage from the inter-
nal regulator supply voltage. It is controlled by the Voltage Regulator Calibration Register
(VREGCR). The voltage regulator is enabled by default at start-up but can be disabled by soft-
ware if an external voltage is provided on the VDDCORE pin. The VREGCR also contains bits to
control the POR18 detector and the POR33 detector.
14.5.8.1
Register protection
To prevent unexpected writes to VREGCR due to software bugs, write access to this register is
protected by a locking mechanism. For details please refer to the UNLOCK register description.
To prevent further modifications by software, the content of the VREGCR register can be set as
read-only by writing a one to the Store Final Value bit (VREGCR.SFV). Once this bit is set, soft-
ware can not change the VREGCR content until a Power-on Reset (POR) is applied.
14.5.8.2
Controlling voltage regulator output
The voltage regulator is always enabled at start-up, i.e. after a POR or when waking up from
Shutdown mode. It can be disabled by software by writing a zero to the Enable bit
(VREGCR.EN). This bit is set after a POR. Because of internal synchronization, the voltage reg-
ulator is not immediately enabled or disabled. The actual state of the voltage regulator can be
read from the ON bit (VREGCR.ON).
The voltage regulator output level is controlled by the Select VDD field (SELVDD) in VREGCR.
The default value of this field corresponds to a regulator output voltage of 1.8V. Other values of
this field are not defined, and it is not recommended to change the value of this field.
The Voltage Regulator OK bit (VREGCR.VREGOK) bit indicates when the voltage regulator out-
put has reached the voltage threshold level.
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