ATUC128L3U_14 Datasheet, PDF (262/963 Pages) ATMEL Corporation – High-performance, Low-power 32-bit Atmel

ATUC64/128/256L3/4U
The user must configure the FP frequency by writing to the FPMUL and FPDIV fields of the
FPMUL and FPDIV registers. FPMUL and FPDIV must not be equal to zero and FPDIV must be
greater or equal to FPMUL. This results in the output frequency:
f_FPCLK = f_SRC * FPMUL/ (2*FPDIV)
The CKSEL field can not be changed dynamically but the FPMUL and FPDIV fields can be
changed on-the-fly.
• Jitter description
As described in Figure 14-9, the CLKFP half period lengths are integer multiples of the source
clock period but are not always equals. However the difference between the low level half period
length and the high level half period length is at the most one source clock period.
This induces when FPDIV is not an integer multiple of FPMUL a jitter on the FPCLK. The more
the FPCLK frequency is low, the more the jitter incidence is reduced.
Figure 14-9. Fractional Prescaler Jitter Examples
SRC clock
FMUL= 5
FDIV=5
FPCLK _FMUL=3
FDIV=10
FMUL=7
FDIV=9
14.5.15
Generic Clocks
Rev: 1.1.0.0
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in
the SCIF Module Configuration section. The selected source can optionally be divided by any
even integer up to 512. Each clock can be independently enabled and disabled, and is also
automatically disabled along with peripheral clocks by the Sleep Controller in the Power
Manager.
32142D–06/2013
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